US 12,135,781 B2
Implementing hardware-based memory safety for a graphic processing unit
Aamer Jaleel, Northborough, MA (US); Mohamed Tarek Bnziad Mohamed Hassan, New York, NY (US); and Mark Stephenson, Austin, TX (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Dec. 29, 2021, as Appl. No. 17/565,345.
Claims priority of provisional application 63/237,088, filed on Aug. 25, 2021.
Prior Publication US 2023/0061154 A1, Mar. 2, 2023
Int. Cl. G06F 21/53 (2013.01); G06F 9/44 (2018.01); G06F 9/445 (2018.01); G06F 12/14 (2006.01)
CPC G06F 21/53 (2013.01) [G06F 9/44589 (2013.01); G06F 12/1441 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method comprising, at a device:
maintaining a metadata table having entries for memory allocations made during an execution of compiled source code; and determining, in hardware, a safety of memory access requests during the execution of the compiled source code, utilizing the metadata table, including: when the compiled source code is being executed by a GPU (Graphical Processing Unit), in response to identifying a memory access request within the compiled source code, a hardware load/store unit identifies an associated load/store address included within the memory access request, the hardware load/store unit sends the load/store address to memory safety hardware, and in response to receiving the load/store address the memory safety hardware requests a base address for a hardware memory safety cache from a metadata base register, where the hardware memory safety cache caches recently used data from the metadata table.