US 12,135,680 B2
Dynamic processor architecture control
Khaled Maalej, Paris (FR); Trung Dung Nguyen, Massy (FR); Julien Schmitt, Massy (FR); and Pierre-Emmanuel Bernard, Antony (FR)
Assigned to VSORA, Meudon la Foret (FR)
Appl. No. 16/771,376
Filed by VSORA, Meudon La Foret (FR)
PCT Filed Nov. 27, 2018, PCT No. PCT/FR2018/052995
§ 371(c)(1), (2) Date Jun. 10, 2020,
PCT Pub. No. WO2019/115902, PCT Pub. Date Jun. 20, 2019.
Claims priority of application No. 17 62068 (FR), filed on Dec. 13, 2017.
Prior Publication US 2021/0173809 A1, Jun. 10, 2021
Int. Cl. G06F 15/80 (2006.01); G06F 8/41 (2018.01); G06F 9/445 (2018.01)
CPC G06F 15/80 (2013.01) [G06F 8/447 (2013.01); G06F 8/47 (2013.01); G06F 9/44589 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method for compiling a source code comprising the following steps:
receiving the source code as input,
searching in the source code:
for configuration data imposing an operating architecture of a processor,
for first parts of the source code corresponding to data processing instructions including cascaded sequences of elementary operations, and
for second parts of the source code corresponding to data processing instructions including elementary operations that are independent of one another,
the method further comprising the following step:
compiling the source code into a machine code,
in a first case where at least one configuration datum imposing the operating architecture of the processor has been identified, and
in a second case where the first parts of the source code and the second parts of the source code have been identified, wherein the compiling of the source code into the machine code comprises generating the machine code to include a configuration function based on the second case, said configuration function being arranged to dynamically impose on processing units within the processor executing the machine code an architecture adaptation:
from a single instruction multiple data (SIMD) stream architecture where the processing units within the processor are dynamically configured for the elementary operations that are independent of one another to not directly exchange data, to a multiple instruction single data (MISD) stream architecture for the cascaded sequences of elementary operations where processed data from a first processing unit of the processing units within the processor is copied to a second processing unit of the processing units within the processor, or
from the MISD stream architecture to the SIMD stream architecture.