US 12,135,678 B2
Data link stability detection using computer vision-based data eye analysis
Uttkarsh Wardhan, Bangalore (IN); Vishal Ghorpade, Bangalore (IN); Sanku Mukherjee, Bangalore (IN); Madan Krishnappa, San Diego, CA (US); Sanath Sreekanta, Bangalore (IN); Pankhuri Agarwal, Bangalore (IN); and Santanu Pattanayak, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Appl. No. 18/041,168
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
PCT Filed Apr. 23, 2021, PCT No. PCT/US2021/028852
§ 371(c)(1), (2) Date Feb. 9, 2023,
PCT Pub. No. WO2022/035474, PCT Pub. Date Feb. 17, 2022.
Claims priority of application No. 202041034975 (IN), filed on Aug. 14, 2020.
Prior Publication US 2023/0267096 A1, Aug. 24, 2023
Int. Cl. G06F 15/78 (2006.01); G05B 13/00 (2006.01)
CPC G06F 15/7814 (2013.01) [G05B 13/00 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method for maintaining reliability of a data communication link in a computing device, comprising:
collecting, by a control system, a two-dimensional array of data points representing a data eye on the data communication link;
determining, by a convolutional neural network, a score of the two-dimensional array of data points;
comparing, by the control system, the determined score with a threshold;
initiating, by the control system, an action based on a result of comparing the determined score with the threshold;
counting, by the control system, a number of times a received data value does not match a corresponding transmitted data value under conditions of each combination of reference voltage and clock-data time delay; and
forming, by the control system, the two-dimensional array of data points, each data point corresponding to the number of times a received data value does not match a corresponding transmitted data value, each data point positioned in the array at a unique combination of reference voltage and clock-data time delay.