US 12,135,677 B2
Enhanced SPI controller and SPI controller operating method
Cheng'en Wu, Shanghai (CN); Jeroen Domburg, Shanghai (CN); and Xufeng Xiao, Shanghai (CN)
Assigned to ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD., Shanghai (CN)
Appl. No. 18/031,129
Filed by ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD., Shanghai (CN)
PCT Filed Jun. 29, 2021, PCT No. PCT/CN2021/103232
§ 371(c)(1), (2) Date Apr. 10, 2023,
PCT Pub. No. WO2022/073363, PCT Pub. Date Apr. 14, 2022.
Claims priority of application No. 202011078754.0 (CN), filed on Oct. 10, 2020.
Prior Publication US 2023/0385226 A1, Nov. 30, 2023
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4291 (2013.01) 20 Claims
OG exemplary drawing
 
1. An SPI controller, comprising:
an SPI clock signal generator, configured to generate an SPI clock signal;
a register group configured to store an SPI operating configuration of the SPI controller;
a plurality of SPI pins configured to connect to one or more SPI peripherals; and
an input/output controller configured to perform data input or output between the SPI controller and the SPI peripherals according to the SPI clock signal and the SPI operating configuration; and
an SPI state machine configured to control a working state of the SPI controller;
wherein the SPI controller is electrically coupled via a bus to a CPU, a DMA controller and a system memory located outside the SPI controller; and
the input/output controller is further configured to receive an updated SPI operating configuration from the DMA controller and update the updated SPI operating configuration into the register group between two consecutive SPI transmissions.