US 12,135,668 B2
Asynchronous controller for processing unit
Marco Castellano, Pavia (IT); Francesco Bruni, Mirandola (IT); Luca Gandolfi, Milan (IT); and Marco Leo, Milan (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Nov. 16, 2022, as Appl. No. 18/056,012.
Prior Publication US 2024/0160593 A1, May 16, 2024
Int. Cl. G06F 3/00 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/4068 (2013.01) [G06F 2213/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a synchronous circuit comprising a plurality of processing stages, wherein each processing stage comprises a selection data bus; and
an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit comprises an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further comprises a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit, and wherein the selectable delay comprises a delay matched to a latency of each corresponding different specific instruction in the synchronous circuit.