US 12,135,667 B2
Interface bridge between integrated circuit die
Jeffrey Erik Schulz, Milpitas, CA (US); David W. Mendel, Sunnyvale, CA (US); Dinesh D. Patil, Sunnyvale, CA (US); Gary Brian Wallichs, San Jose, CA (US); Keith Duwel, San Jose, CA (US); and Jakob Raymond Jones, San Jose, CA (US)
Assigned to ALTERA CORPORATION, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 31, 2023, as Appl. No. 18/327,043.
Application 18/327,043 is a continuation of application No. 17/561,918, filed on Dec. 24, 2021, granted, now 11,693,810.
Application 17/561,918 is a continuation of application No. 17/131,404, filed on Dec. 22, 2020, granted, now 11,237,998, issued on Feb. 1, 2022.
Application 17/131,404 is a continuation of application No. 16/536,147, filed on Aug. 8, 2019, granted, now 11,100,029, issued on Aug. 24, 2021.
Application 16/536,147 is a continuation of application No. 15/392,225, filed on Dec. 28, 2016, granted, now 10,445,278, issued on Oct. 15, 2019.
Prior Publication US 2023/0305982 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H03K 19/173 (2006.01); H04W 56/00 (2009.01)
CPC G06F 13/4045 (2013.01) [G06F 13/385 (2013.01); G06F 13/42 (2013.01); G06F 13/4291 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H03K 19/1736 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1431 (2013.01); H04W 56/0015 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a substrate;
a first die mounted on the substrate, the first die comprising a first plurality of input/output (IO) interfaces;
a plurality of second dies mounted on the substrate, wherein at least one die of the plurality of second dies comprises including an IO interface of a second plurality of IO interfaces;
a plurality of chip-to-chip interconnects formed within the substrate to couple the first plurality of IO interfaces to the second plurality of IO interfaces; and
a management subsystem configurable to utilize the plurality of chip-to-chip interconnects to communicate status and control information between the first die and the plurality of second dies.