US 12,135,664 B2
Compute sled providing high speed storage access through a PCI express fabric between compute nodes and a storage server
Roelof Roderick Colenbrander, Costa Mesa, CA (US)
Assigned to Sony Interactive Entertainment Inc., Tokyo (JP)
Filed by Sony Interactive Entertainment Inc., Tokyo (JP)
Filed on May 9, 2023, as Appl. No. 18/314,693.
Application 18/314,693 is a continuation of application No. 17/175,636, filed on Feb. 13, 2021, granted, now 11,645,218.
Claims priority of provisional application 62/977,138, filed on Feb. 14, 2020.
Prior Publication US 2023/0273889 A1, Aug. 31, 2023
Int. Cl. G06F 13/36 (2006.01); G06F 13/16 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H04L 49/351 (2022.01); H04L 67/1097 (2022.01)
CPC G06F 13/382 (2013.01) [G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4221 (2013.01); G06F 13/4282 (2013.01); H04L 49/351 (2013.01); H04L 67/1097 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/3808 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A compute sled comprising:
a plurality of compute nodes, wherein each of the plurality of compute nodes includes one or more Peripheral Component Interconnect Express (PCIe) lanes and one or more universal asynchronous receiver transmitter (UART) connections configured for transmitting and receiving serial data;
a sled level PCIe switch electrically coupled to the plurality of compute nodes, the sled level PCIe switch including a plurality of incoming lanes and a plurality of outgoing lanes,
wherein the plurality of incoming lanes is greater than the plurality of outgoing lanes,
wherein the one or more PCIe lanes of the each of the plurality of compute nodes are electrically coupled to the plurality of incoming lanes,
wherein the plurality of outgoing lanes is electrically coupled to network storage via an array-level PCIe switch; and
a board management controller (BMC) electrically coupled to the one or more UART connections of the each of the plurality of compute nodes, the BMC configured for management of one or more components of the each of the plurality of compute nodes using a plurality of UART signals delivered over the one or more UART connections to the each of the plurality of compute nodes, wherein the one or more UART connections is independent of the one or more PCIe lanes for the each of the plurality of compute nodes.