US 12,135,660 B2
Integrated circuit device with embedded programmable logic
Arifur Rahman, San Jose, CA (US); and Bernhard Friebe, La Honda, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by ALTERA CORPORATION, San Jose, CA (US)
Filed on Mar. 22, 2022, as Appl. No. 17/701,511.
Application 17/701,511 is a continuation of application No. 16/933,628, filed on Jul. 20, 2020, granted, now 11,281,605.
Application 16/933,628 is a continuation of application No. 16/378,356, filed on Apr. 8, 2019, granted, now 10,719,460, issued on Jul. 21, 2020.
Application 16/378,356 is a continuation of application No. 15/422,310, filed on Feb. 1, 2017, granted, now 10,296,474, issued on May 21, 2019.
Application 15/422,310 is a continuation of application No. 14/602,131, filed on Jan. 21, 2015, granted, now 9,589,612, issued on Mar. 7, 2017.
Application 14/602,131 is a continuation of application No. 13/913,096, filed on Jun. 7, 2013, granted, now 9,136,842, issued on Sep. 15, 2015.
Prior Publication US 2022/0214982 A1, Jul. 7, 2022
Int. Cl. H01L 23/538 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G11C 7/22 (2006.01); G11C 8/00 (2006.01); G11C 29/12 (2006.01); H01L 25/18 (2023.01); H03K 19/003 (2006.01); H03K 19/173 (2006.01); H03K 19/1776 (2020.01); G06F 1/00 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H03K 19/00 (2006.01)
CPC G06F 13/1689 (2013.01) [G06F 13/4068 (2013.01); G06F 13/42 (2013.01); G11C 7/22 (2013.01); G11C 8/00 (2013.01); G11C 29/12 (2013.01); H01L 23/5381 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 25/18 (2013.01); H03K 19/003 (2013.01); H03K 19/1733 (2013.01); H03K 19/1776 (2013.01); G06F 1/00 (2013.01); H01L 24/17 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01); H03K 19/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory integrated circuit, comprising:
a primary circuit configured to implement a first memory operation; and
an embedded programmable logic configured to implement a second memory operation, wherein the second memory operation is configured to adjust functionality of the primary circuit.