| CPC G06F 12/0891 (2013.01) [G06F 12/1027 (2013.01)] | 35 Claims |
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1. A processor-based device, comprising:
a plurality of processors, comprising a remote processor and an issuing processor;
the remote processor comprising:
a translation lookaside buffer (TLB) comprising a plurality of TLB entries; and
a Data Synchronization Barrier (DSB) filter circuit corresponding to the TLB, the DSB filter circuit comprising filtering criteria; and
the remote processor configured to:
receive, from the issuing processor of the plurality of processors, a TLB invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of the plurality of TLB entries;
receive, from the issuing processor, a DSB instruction;
determine, using the DSB filter circuit, whether the TLBI instruction satisfies the filtering criteria; and
responsive to determining that the TLBI instruction satisfies the filtering criteria:
forego execution of a DSB operation corresponding to the DSB instruction by the remote processor; and
issue an early DSB acknowledgement to the issuing processor.
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