US 12,135,651 B2
Cache systems with different address domains
Olof Henrik Uhrenholt, Lund (SE)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Dec. 9, 2022, as Appl. No. 18/064,044.
Claims priority of application No. 2118624 (GB), filed on Dec. 21, 2021; application No. 2118626 (GB), filed on Dec. 21, 2021; and application No. 2118631 (GB), filed on Dec. 21, 2021.
Prior Publication US 2023/0195630 A1, Jun. 22, 2023
Int. Cl. G06F 12/0891 (2016.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0808 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0824 (2013.01); G06F 2212/1016 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of operating a cache system that comprises a cache operable to cache data stored in memory for a processor, wherein the cache is operable to cache uncompressed data stored in memory, and to cache in decompressed form compressed data stored in memory;
the method comprising:
addressing entries in the cache that cache uncompressed data using a first address domain; and
addressing entries in the cache that cache compressed data in decompressed form using a second, different address domain;
wherein plural addresses in the second address domain translate to fewer addresses in the first address domain.