US 12,135,650 B2
On-chip packet caching apparatus, method and computer-readable medium using idle address management module
Weichao Liang, Guangdong (CN); Jianfeng Zhong, Guangdong (CN); Da Hu, Guangdong (CN); Changsheng Chen, Guangdong (CN); Dongguo Xu, Guangdong (CN); and Jianfeng Lu, Guangdong (CN)
Assigned to SANECHIPS TECHNOLOGY CO., LTD., Guangdong (CN)
Appl. No. 17/919,345
Filed by ZTE CORPORATION, Guangdong (CN)
PCT Filed Apr. 16, 2021, PCT No. PCT/CN2021/087872
§ 371(c)(1), (2) Date Oct. 17, 2022,
PCT Pub. No. WO2021/209051, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 202010306644.9 (CN), filed on Apr. 17, 2020.
Prior Publication US 2023/0195637 A1, Jun. 22, 2023
Int. Cl. G06F 12/0868 (2016.01); G06F 12/0817 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0868 (2013.01) [G06F 12/0824 (2013.01); G06F 13/1673 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An on-chip cache apparatus, comprising:
a read-write processing module, a cache module and a memory module, wherein the read-write processing module is connected with the cache module and the memory module respectively, and is configured to store packets into the cache module and the memory module, read packets stored in the cache module and the memory module, and transfer packets cached in the cache module to the memory module for storing;
the cache module is connected with the memory module through the read-write processing module, and comprises at least one cache register configured to temporarily cache the packets; and
the memory module is connected with the read-write processing module, and is configured to store the packets cached in the cache module;
wherein the on-chip cache apparatus further comprises:
an idle address management module connected with the read-write processing module and configured to manage idle row addresses in the memory module, each first-in-first-out buffer in the idle address management module stores the idle row addresses, a depth of the first-in-first-out buffer in the idle address management module is same as a depth of a random access memory in the memory module, wherein the depth of the random access memory is determined according to a packet transmission rate of the random access memory in the memory module and a reserved speed-up ratio.