US 12,135,649 B2
System for prefetching data into a cache
Ramkumar Srinivasan, Saratoga, CA (US); Gerard Williams, Newport Coast, CA (US); and Varun Palivela, Santa Clara, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 14, 2023, as Appl. No. 18/169,118.
Claims priority of provisional application 63/386,224, filed on Dec. 6, 2022.
Prior Publication US 2024/0184700 A1, Jun. 6, 2024
Int. Cl. G06F 12/0862 (2016.01); G06F 12/02 (2006.01); G06F 12/123 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 12/0238 (2013.01); G06F 12/123 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A prefetch system for prefetching data into a cache, comprising a prefetch control circuit configured to:
in response to receiving a memory operation comprising a first address of the memory operation and a first data memory address:
access a first fetch entry of a plurality of fetch entries in a fetch table based on the first address of the memory operation;
access a first delta entry of a plurality of delta entries in a delta table based on the first address of the memory operation and a set of fetched memory deltas in the first fetch entry;
determine whether a difference between the first data memory address and a last fetched address in the first fetch entry matches a next delta in the first delta entry;
adjust a confidence value in the first delta entry; and
the prefetch control circuit further configured, in response to a signal, to:
select a second fetch entry in the fetch table;
access a second delta entry in the delta table based on a second address for a second memory operation in the second fetch entry and a set of prefetched memory deltas in the second fetch entry; and
determine a prefetch address for prefetching by adding a next memory delta in the second delta entry to a last prefetched address in the second fetch entry.