US 12,135,646 B2
Cache coherence shared state suppression
Abhijeet Ashok Chachad, Plano, TX (US); David Matthew Thompson, Dallas, TX (US); Timothy David Anderson, University Park, TX (US); and Kai Chirca, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 30, 2023, as Appl. No. 18/325,190.
Application 18/325,190 is a continuation of application No. 17/666,196, filed on Feb. 7, 2022, granted, now 11,675,700.
Application 17/666,196 is a continuation of application No. 16/882,257, filed on May 22, 2020, granted, now 11,243,883, issued on Feb. 8, 2022.
Claims priority of provisional application 62/852,416, filed on May 24, 2019.
Prior Publication US 2023/0297506 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/084 (2016.01); G06F 12/0895 (2016.01); G06F 12/128 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0811 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/3867 (2013.01); G06F 9/467 (2013.01); G06F 9/544 (2013.01); G06F 9/546 (2013.01); G06F 11/3037 (2013.01); G06F 12/0808 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/084 (2013.01); G06F 12/0895 (2013.01); G06F 12/128 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a processor core;
a level-one (L1) cache controller coupled to the processor core;
a level-two (L2) cache controller coupled to the L1 cache controller; and
an L2 cache memory coupled to the L2 cache controller, wherein:
the processor core is configured to cause the L1 cache controller to provide a first cache request to the L2 cache controller;
the first cache request is associated with a first coherence state;
the L2 cache controller includes a configuration register configured to store a configuration value that specifies whether the L2 cache controller is configured to operate in a first mode in which the first coherence state is supported or a second mode in which the first coherence state is not supported; and
the L2 cache controller is configured to determine whether to generate, in response to the first cache request, a second cache request associated with the first coherence state or associated with a second coherence state based on the configuration value.