US 12,135,645 B2
Nonvolatile physical memory with DRAM cache
Frederick A. Ware, Los Altos Hills, CA (US); John Eric Linstadt, Palo Alto, CA (US); and Christopher Haywood, Cary, NC (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on May 30, 2023, as Appl. No. 18/203,569.
Application 18/203,569 is a continuation of application No. 17/702,505, filed on Mar. 23, 2022, granted, now 11,714,752.
Application 17/702,505 is a continuation of application No. 16/652,234, granted, now 11,301,378, issued on Apr. 12, 2022, previously published as PCT/US2018/054206, filed on Oct. 3, 2018.
Claims priority of provisional application 62/609,925, filed on Dec. 22, 2017.
Claims priority of provisional application 62/571,395, filed on Oct. 12, 2017.
Prior Publication US 2023/0359559 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0804 (2016.01); G06F 12/12 (2016.01); G11C 14/00 (2006.01)
CPC G06F 12/0804 (2013.01) [G06F 12/12 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/205 (2013.01); G11C 14/0018 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controller to manage memory-access requests, the controller comprising:
a nonvolatile memory (NVM) interface to a NVM with physical memory space divided into NVM cache lines; and
a dynamic, random-access memory (DRAM) interface to a DRAM divided into DRAM cache lines;
the controller to allocate an erased one of the NVM cache lines to one of the DRAM cache lines and write data, a dirty bit, and a state bit to the one of the DRAM cache lines, the state bit indicating the data is absent from the NVM.