| CPC G06F 12/0802 (2013.01) [G11C 5/04 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01)] | 20 Claims |
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1. A memory module operable in a computer system having a memory controller and a system bus, the system bus including a set of address/control (C/A) signal lines and a plurality of sets of data/strobe signal lines, the memory module comprising:
a printed circuit board (PCB) including connectors along an edge thereof for connecting to the set of C/A signal lines and the plurality of sets of data/strobe signal lines;
a plurality of buffer circuits mounted on the PCB, each buffer circuit of the plurality of buffer circuits corresponding to a respective set of the plurality of sets of data/strobe signal lines and including one or more configuration registers, one or more delay control circuit, and one or more delay circuits, the one or more delay circuits to adjust timing of one or more signals in the each buffer circuit of the plurality of buffer circuits;
a module control circuit mounted on the PCB and configurable to receive from the memory controller input address and control (C/A) signals associated with a read or write operation via the set of C/A signal lines, to output registered C/A signals associated with the read or write operation via first module control signal lines, and to output buffer control signals associated with the memory read or write operation via second module control signal lines;
memory devices mounted on the PCB and organized in ranks, the memory devices including a plurality of groups of memory devices, a respective group of memory devices corresponding to a respective buffer circuit of the plurality of buffer circuits and including at least one respective memory device in each of the ranks;
wherein:
in response to the registered C/A signals, at least one first memory device in a first group of the plurality of groups of memory devices is configured to receive or output first data/strobe signals;
in response to the buffer control signals, a first buffer circuit of the plurality of buffer circuits is configured to output or receive the first data/strobe signals and to receive or output second data/strobe signals, the second data/strobe signals corresponding, respectively, to the first data/strobe signals and being communicated between the memory module and the memory controller via a first set of data/strobe signal lines of the plurality of sets of data/strobe signal lines;
at least one delay circuit of the one or more delay circuits in the first buffer circuit is configured to delay at least one signal in the first buffer circuit based on a first delay and a second delay, each of the at least one signal being related to a corresponding signal in the first data/strobe signals or the second data/strobe signals;
the memory module is operable in a configuration mode, and the first delay is programed into and stored in at least one configuration register of the one or more configuration registers in the first buffer circuit in response to mode register command signals received from the memory controller via the set of C/A signal lines during the configuration mode; and
the second delay is determined by at least one delay control circuit of the one or more delay control circuits in the first buffer circuit while the memory module is not operating in the configuration mode.
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