US 12,135,643 B2
Sequestered memory for selective storage of metadata corresponding to cached data
Michael Kounavis, Portland, OR (US); Siddhartha Chhabra, Portland, OR (US); and David M. Durham, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 12, 2020, as Appl. No. 17/096,274.
Prior Publication US 2022/0147453 A1, May 12, 2022
Int. Cl. G06F 12/0802 (2016.01); H04L 9/32 (2006.01)
CPC G06F 12/0802 (2013.01) [H04L 9/32 (2013.01); G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
first circuitry to detect that data is to be cached, and to perform an evaluation, based on the data and a predefined criteria, of whether a line of a cache is able to accommodate a first representation of both the data and metadata corresponding to the data; and
second circuitry coupled to the first circuitry, the second circuitry to detect, based on the evaluation, either one of:
a first condition wherein the line is able to accommodate the first representation; or
a second condition wherein the line is unable to accommodate the first representation;
wherein, based on the first condition, the second circuitry is to:
generate the first representation based on the data and the metadata; and
store the first representation to the line; and
wherein, based on the second condition, the second circuitry is to:
generate a second representation based on the data;
store the second representation to the line; and
store the metadata to a sequestered memory region which is external to the cache.