| CPC G06F 12/08 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 2213/28 (2013.01)] | 10 Claims |
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1. A semiconductor device executing a neural network processing, comprising:
single or plural memories configured to store weight parameters and pixel data;
“m” multiplier groups each configured to include “n” multipliers in which each of “n” and “m” is an integer number that is equal to or larger than 2;
a weight parameter buffer configured to output the stored “n×m” weight parameters to the “n×m” multipliers, respectively;
a data input buffer configured to output the stored “n×m” pixel data to the “n×m” multipliers, respectively;
a first Direct Memory Access (DMA) controller configured to transfer the “n×m” weight parameters from the memory to the weight parameter buffer;
a second Direct Memory Access (DMA) controller configured to transfer the “n×m” pixel data from the memory to the data input buffer; and
a group controller configured to control each “m” multiplier groups to be enabled/disabled,
wherein the group controller is configured to
detect a zero weight parameter having a zero value among the “n×m” weight parameters to be transferred to the weight parameter buffer, and,
when receiving the zero weight parameter as its input, exchange the “n×m” weight parameters to be transferred to the weight parameter buffer so that all multiplication results of the “n” multipliers included in a target multiplier group that is one of the “m” multiplier groups are zero,
control the target multiplier group to be disabled, and
exchange the “n×m” pixel data to be transferred to the data input buffer, based on the exchange of the “n×m” weight parameters.
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