US 12,135,641 B2
Controlling method of a memory card
Takashi Wakutsu, Kamakura (JP); Shuichi Sakurai, Yokohama (JP); Kuniaki Ito, Funabashi (JP); and Yasufumi Tsumagari, Kawasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Oct. 27, 2023, as Appl. No. 18/496,395.
Application 18/496,395 is a continuation of application No. 17/885,466, filed on Aug. 10, 2022, granted, now 11,836,075.
Application 17/885,466 is a continuation of application No. 17/066,906, filed on Oct. 9, 2020, granted, now 11,442,853, issued on Sep. 13, 2022.
Application 17/066,906 is a continuation of application No. 16/415,095, filed on May 17, 2019, granted, now 10,838,856, issued on Nov. 17, 2020.
Application 16/415,095 is a continuation of application No. 16/032,434, filed on Jul. 11, 2018, granted, now 10,380,017, issued on Aug. 13, 2019.
Application 16/032,434 is a continuation of application No. 15/680,299, filed on Aug. 18, 2017, granted, now 10,042,757, issued on Aug. 7, 2018.
Application 15/680,299 is a continuation of application No. 15/188,533, filed on Jun. 21, 2016, granted, now 9,760,483, issued on Sep. 12, 2017.
Application 15/188,533 is a continuation of application No. 13/958,274, filed on Aug. 2, 2013, granted, now 9,501,399, issued on Nov. 22, 2016.
Application 13/958,274 is a continuation of application No. PCT/JP2011/071773, filed on Sep. 16, 2011.
Claims priority of application No. 2011-023218 (JP), filed on Feb. 4, 2011; and application No. 2011-045614 (JP), filed on Mar. 2, 2011.
Prior Publication US 2024/0061771 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 13/38 (2006.01); G06K 19/077 (2006.01); H04B 1/3827 (2015.01); H04M 1/02 (2006.01); H04M 1/72412 (2021.01); H04W 12/47 (2021.01)
CPC G06F 12/0246 (2013.01) [G06F 3/06 (2013.01); G06F 3/0607 (2013.01); G06F 3/061 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0664 (2013.01); G06F 3/067 (2013.01); G06F 3/0679 (2013.01); G06F 13/385 (2013.01); G06K 19/07732 (2013.01); G06K 19/07733 (2013.01); G06K 19/07749 (2013.01); H04B 1/3827 (2013.01); H04M 1/72412 (2021.01); G06F 2213/3804 (2013.01); G06F 2213/3814 (2013.01); H04M 1/0254 (2013.01); H04W 12/47 (2021.01)] 16 Claims
OG exemplary drawing
 
1. A method of controlling a memory system which is connectable to a host device and an external device other than the host device, the memory system including a host interface to connect to the host device, a wireless network interface to connect to the external device, a nonvolatile memory configured to store data from the host device and the external device, and a register including a plurality of pages, a first data port, and a second data port, a specific page of the register storing information indicating a number of one or more functions, the method comprising:
controlling the nonvolatile memory to write and read data in response to a request from the host device via the host interface;
transmitting data stored in the nonvolatile memory to the external device or receiving data from the external device, via the wireless network interface with a wireless communication;
processing a first command to read data from the register;
processing a second command to write data to the register; and
setting, in the register, a first address region to which a first function of the wireless communication is assigned and a second address region to which a second function of the wireless communication is assigned, the first address region and the second address region being located at different pages of the register, the first data port being associated with the first function, the second data port being associated with the second function.