US 12,135,624 B2
Circuits, systems, and methods for ECC fault detection
Mohamed Soubhi, Dusseldorf (DE)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Dec. 14, 2022, as Appl. No. 18/065,813.
Prior Publication US 2024/0202086 A1, Jun. 20, 2024
Int. Cl. G06F 11/22 (2006.01); H03M 13/01 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/2215 (2013.01) [H03M 13/015 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A detection circuit for detecting faulty operation of an error correction code (ECC) decoder that is configured for diagnosing whether an error has occurred in input data to the ECC decoder, wherein the ECC decoder is further configured for outputting an error detection signal indicative of whether the error has been detected and potentially corrected by the ECC decoder and output data based on the input data, and wherein the detection circuit comprises:
a first stage configured to generate a first check signal indicative of whether there is a mismatch between the input data and the output data of the ECC decoder; and
a second stage configured to generate a second check signal indicative of whether faulty operation of the ECC decoder has been detected based on the first check signal and the error detection signal of the ECC decoder,
wherein the ECC decoder comprises a data correction component configured for correcting the error detected by the ECC decoder, and
wherein the second check signal generated by the second stage indicates that the data correction component of the ECC decoder is faulty, if the first check signal indicates that there is the mismatch between the input data and the output data of the ECC decoder while the error detection signal of the ECC decoder indicates that no error has been detected by the ECC decoder.