US 12,135,610 B2
ECC configuration in memories
Graziano Mirichigni, Vimercate (IT); Christophe Laurent, Agrate Brianza (IT); and Riccardo Muzzetto, Arcore (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/802,053
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Sep. 23, 2021, PCT No. PCT/IB2021/022216
§ 371(c)(1), (2) Date Mar. 30, 2023,
PCT Pub. No. WO2023/047149, PCT Pub. Date Mar. 30, 2023.
Prior Publication US 2024/0211347 A1, Jun. 27, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 11/0703 (2013.01); G06F 11/1016 (2013.01); G06F 11/1024 (2013.01); G06F 11/1044 (2013.01); G06F 11/1068 (2013.01); G06F 11/1096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for operating an array of memory cells, the method comprising:
storing user data in a plurality of memory cells of the array;
storing parity data associated with the user data in a plurality of parity cells of the array; and
based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by:
updating a first register, the first register storing values which indicate a particular ECC correction capability and/or a particular ECC granularity to be applied to the memory cells based on a current status of the memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the particular ECC correction capability and/or the particular ECC granularity to be applied to the memory cells; and
based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity; and
wherein the method further comprises updating a second register according to the varied ECC correction capability and/or ECC granularity, the second register storing values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof.