US 12,135,608 B2
Memory address protection circuit including an error detection circuit and method of operating same
Saman M. I. Adham, Hsinchu (TW); Ramin Shariat-Yazdi, Hsinchu (TW); and Shih-Lien Linus Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 19, 2023, as Appl. No. 18/355,222.
Application 18/355,222 is a continuation of application No. 17/855,412, filed on Jun. 30, 2022, granted, now 11,714,705.
Application 17/855,412 is a continuation of application No. 16/989,018, filed on Aug. 10, 2020, granted, now 11,379,298, issued on Jul. 5, 2022.
Application 16/989,018 is a continuation of application No. 15/622,408, filed on Jun. 14, 2017, granted, now 10,740,174, issued on Aug. 11, 2020.
Claims priority of provisional application 62/427,684, filed on Nov. 29, 2016.
Prior Publication US 2023/0385145 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/00 (2006.01); G06F 12/00 (2006.01); G06F 12/14 (2006.01)
CPC G06F 11/1016 (2013.01) [G06F 12/14 (2013.01); G06F 2212/1052 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a memory configured to store a data unit and a set of information, the set of information being based on a write address associated with the stored data unit, the memory being further configured to be free of storing the write address;
an address port configured to receive a read address for the stored data unit;
a first decoding circuit configured to generate a decoded write address from the read address and the set of information; and
an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.