US 12,135,607 B2
Hardware-efficient PAM-3 encoder and decoder
Gautam Bhatia, San Mateo, CA (US); Sunil Sudhakaran, Brisbane, CA (US); and Kyutaeg Oh, San Ramon, CA (US)
Assigned to NVIDIA Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Mar. 20, 2023, as Appl. No. 18/186,464.
Application 18/186,464 is a continuation in part of application No. 17/931,062, filed on Sep. 9, 2022.
Claims priority of provisional application 63/330,315, filed on Apr. 13, 2022.
Claims priority of provisional application 63/329,838, filed on Apr. 11, 2022.
Claims priority of provisional application 63/328,172, filed on Apr. 6, 2022.
Claims priority of provisional application 63/321,534, filed on Mar. 18, 2022.
Prior Publication US 2023/0297466 A1, Sep. 21, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 11/0787 (2013.01); G06F 11/1068 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits, the transceiver comprising:
communication channels comprising a plurality of data channels and an error correction channel;
an encoder configured to:
apply 11b7s encoding to a first plurality of the data bits to generate first PAM-3 symbols on some or all of the communication channels; and
apply 3b2s encoding to the meta-data bits to generate second PAM-3 symbols on some or all of the communication channels, wherein a Hamming distance between any pair of codes for the second PAM-3 symbols is greater than or equal to a Hamming distance of a binary code for the meta-data bits corresponding to the pair of codes.