US 12,135,602 B2
Global integrated circuit power control
Doron Rajwan, Rishon LeZion (IL); Inder M. Sodhi, Palo Alto, CA (US); Keith Cox, Sunnyvale, CA (US); Jung Wook Cho, Cupertino, CA (US); Kevin I. Park, San Francisco, CA (US); and Tal Kuzi, Tel Aviv (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 11, 2022, as Appl. No. 17/573,268.
Claims priority of provisional application 63/247,854, filed on Sep. 24, 2021.
Prior Publication US 2023/0101217 A1, Mar. 30, 2023
Int. Cl. G06F 1/3296 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01)
CPC G06F 1/3296 (2013.01) [G06F 1/324 (2013.01); G06F 1/3243 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of component circuits, wherein a given component circuit of the plurality of component circuits is included in one of a plurality of independent power domains, and wherein the plurality of component circuits comprise respective rate control circuits and respective power control circuits; and
a power splitter circuit coupled to the plurality of component circuits, wherein:
the power splitter circuit is configured to allocate power to the plurality of component circuits from a power budget for the system;
the power splitter circuit is configured to communicate respective indications of the allocated power to the respective rate control circuits;
the respective rate control circuits are configured to manage power consumption in the corresponding component circuits based on the respective indication of the allocated power provided to the respective rate control circuits; and
the respective power control circuits are configured to limit power consumption within the corresponding component circuits based on one or more respective inputs received from the respective rate control circuits, wherein a first of the power control circuits is configured to implement a first set of power management mechanisms specific to a first one of the component circuits, and wherein a second of the power control circuits is configured to implement a second, different set of power management mechanisms specific to a second one of the component circuits; and
wherein the component circuits and the power splitter circuit are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.