US 12,135,600 B2
Power management in memory
Frank F. Ross, Boise, ID (US); and Matthew A. Prather, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 20, 2021, as Appl. No. 17/479,922.
Application 17/479,922 is a continuation of application No. 16/290,181, filed on Mar. 1, 2019, granted, now 11,126,251.
Prior Publication US 2022/0004245 A1, Jan. 6, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 3/06 (2006.01); G11C 5/14 (2006.01)
CPC G06F 1/3275 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0647 (2013.01); G06F 3/0673 (2013.01); G11C 5/147 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first memory device;
a second memory device coupled to the first memory device;
a register clock driver coupled to the first memory device; and
a controller coupled to the register clock driver, wherein the controller is configured to send a command to the first memory device via the register clock driver, and wherein the controller comprises:
a power management component coupled to the first memory device and the second memory device, wherein the power management component is configured to:
receive an input signal;
convert the input signal by increasing a voltage of the input signal into a first signal to be compatible with the first memory device being a particular type of memory device;
convert the input signal by decreasing a voltage of the input signal into a second signal to save power and to be compatible with the second memory device being a different particular type of memory device; and
transmit the first signal to the first memory device and the second signal to the second memory device.