US 12,135,597 B2
Adaptive lower power state entry and exit
Ang Li, Coquitlam (CA)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 28, 2020, as Appl. No. 16/886,694.
Prior Publication US 2020/0310517 A1, Oct. 1, 2020
Int. Cl. G06F 1/32 (2019.01); G06F 1/14 (2006.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01); G06F 9/46 (2006.01); G06F 13/38 (2006.01)
CPC G06F 1/3206 (2013.01) [G06F 1/14 (2013.01); G06F 1/324 (2013.01); G06F 9/466 (2013.01); G06F 13/385 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an upstream port to send information across a link;
power management circuitry to:
determine that an active state power management (ASPM) link state change condition is satisfied, and
change an APSM link state for the link based on the ASPM link state change condition being satisfied;
ASPM analysis logic to identify an event occurrence based on analyzing a last transaction layer packet (TLP) received prior to the ASPM link change condition being satisfied; and
ASPM tuning logic to tune the ASPM link state change condition based on identifying the occurrence of the event;
wherein the upstream port is to operate according to the ASPM link state.