US 12,135,596 B2
Fast bleed of power rails
James L. Petivan, III, Austin, TX (US); Yun Guo, Round Rock, TX (US); Isaac Q. Wang, Austin, TX (US); Hang Li, Austin, TX (US); Ronald Paul Rudiak, Austin, TX (US); and Justin Whittenberg, Austin, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Oct. 26, 2022, as Appl. No. 17/973,943.
Prior Publication US 2024/0143057 A1, May 2, 2024
Int. Cl. G06F 1/30 (2006.01); H02M 1/00 (2007.01); H02M 1/088 (2006.01); H02M 3/155 (2006.01); H02M 3/156 (2006.01); H03K 3/017 (2006.01)
CPC G06F 1/305 (2013.01) [H02M 1/0032 (2021.05); H02M 1/0045 (2021.05); H02M 1/088 (2013.01); H02M 3/155 (2013.01); H03K 3/017 (2013.01); H02M 3/156 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A voltage regulator system of an information handling system, the voltage regulator system comprising:
a Smart Power Stage (SPS) including a high-side transistor and a low-side transistor; and
a voltage regulator controller to communicate with the high-side and low-side transistors of the SPS, the voltage regulator controller to:
detect a normal power down of the information handling system;
set a bleed state for the SPS to a first state;
based on the bleed state being set to the first state, provide a first control voltage to the low-side transistor and a second control voltage to the high-side transistor,
wherein the first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region; and
in response to a predetermined amount of time expiring, enter the SPS in an idle mode.