US 12,135,581 B2
System, method, and apparatus for SRIS mode selection for PCIE
David J. Harriman, Portland, OR (US); Debendra Das Sharma, Saratoga, CA (US); Daniel S. Froelich, Portland, OR (US); and Sean O. Stalley, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 28, 2022, as Appl. No. 17/955,234.
Application 17/955,234 is a continuation of application No. 15/920,249, filed on Mar. 13, 2018, granted, now 11,630,480.
Claims priority of provisional application 62/568,730, filed on Oct. 5, 2017.
Prior Publication US 2023/0022948 A1, Jan. 26, 2023
Int. Cl. G06F 1/14 (2006.01); G06F 13/42 (2006.01); H04B 1/7073 (2011.01); H04L 69/14 (2022.01)
CPC G06F 1/14 (2013.01) [G06F 13/4221 (2013.01); H04B 1/7073 (2013.01); G06F 2213/0026 (2013.01); H04B 2201/70718 (2013.01); H04B 2201/7073 (2013.01); H04L 69/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a port to couple the device to another device via a link; and
control logic to:
determine a clocking architecture supported by the another device; and
set a clocking architecture to be used on the link by setting one or more bits in a Peripheral Component Interconnect Express (PCIe) link control register, wherein the control logic is to:
set the clocking architecture to a separate reference clock with independent spread spectrum clocking (SRIS) architecture by setting a bit in the PCIe link control register to 1; and
set the clocking architecture to a non-SRIS architecture by setting the bit in the PCIe link control register to 0;
wherein the device is to send information to the another device via the link using the set clocking architecture.