US 12,135,578 B2
Clock distribution circuit with clock tree circuit and filter
Ark-Chew Wong, Irvine, CA (US); Richard Dennis Alexander, Lake Forest, CA (US); and Clifford N. Duong, Buena Park, CA (US)
Assigned to JARIET TECHNOLOGIES, INC., Redondo Beach, CA (US)
Filed by JARIET TECHNOLOGIES, INC., Redondo Beach, CA (US)
Filed on Jan. 19, 2023, as Appl. No. 18/099,215.
Application 18/099,215 is a continuation of application No. 17/023,198, filed on Sep. 16, 2020, granted, now 11,586,241.
Application 17/023,198 is a continuation of application No. 15/999,339, granted, now 10,802,533, issued on Oct. 13, 2020, previously published as PCT/US2017/018465, filed on Feb. 17, 2017.
Claims priority of provisional application 62/296,547, filed on Feb. 17, 2016.
Prior Publication US 2023/0152842 A1, May 18, 2023
Int. Cl. G06F 1/04 (2006.01); G06F 1/06 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 1/08 (2006.01); G06F 1/3203 (2019.01)
CPC G06F 1/10 (2013.01) [G06F 1/04 (2013.01); G06F 1/06 (2013.01); G06F 1/12 (2013.01); G06F 1/08 (2013.01); G06F 1/3203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock distribution circuit, comprising:
a clock tree circuit comprising at least one clock buffer circuit, the clock tree circuit being configured to receive a first clock signal and to generate a second clock signal based on the first clock signal; and
a low-pass filter configured to receive the second clock signal and to provide a third clock signal to one or more load circuits,
wherein:
the low-pass filter comprises a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap and is configurable to resonate with parasitic capacitance associated with the one or more load circuits;
a first high-pass filter is integrated with the clock tree circuit;
the at least one clock buffer circuit comprises a first buffer circuit that is within an inner portion of the clock tree circuit; and
the first high-pass filter is within the inner portion of the clock tree circuit and is directly coupled to the first buffer circuit within the inner portion of the clock tree circuit.