US 12,135,577 B2
Low power and high speed scan dump
Nehal Patel, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Nov. 18, 2022, as Appl. No. 17/990,566.
Prior Publication US 2024/0168513 A1, May 23, 2024
Int. Cl. G06F 1/10 (2006.01)
CPC G06F 1/10 (2013.01) 20 Claims
OG exemplary drawing
 
17. A system, comprising:
a scan dump controller; and
a scan dump network configured to be controlled by the scan dump controller, the scan dump network including:
a first clock domain including a first plurality of data elements; and
a second clock domain including a second plurality of data elements,
wherein the first clock domain is configured to clock gate the first plurality of data elements and to cause data to output from the first plurality of data elements;
wherein the second clock domain is configured to cause the second plurality of data elements to output and to clock gate the second plurality of data elements; and
wherein the data output from the plurality of data elements of the first clock domain flows through the second clock domain operating in bypass mode.