US 12,135,576 B2
Optimal timer array
Gerald Alcorn, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Aug. 18, 2023, as Appl. No. 18/452,193.
Application 18/452,193 is a continuation of application No. 17/182,148, filed on Feb. 22, 2021, granted, now 11,768,515.
Prior Publication US 2024/0019892 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/08 (2006.01); G05B 19/045 (2006.01); H03K 19/17704 (2020.01)
CPC G06F 1/08 (2013.01) [G05B 19/045 (2013.01); H03K 19/17716 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A digital circuit, comprising:
a timer array configured to generate a plurality of timed triggers, the timer array comprising:
a reference counter operating from a reference clock;
a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a respective target offset value of the reference counter; and
a set valid flag logic block that is configured to:
set a respective valid flag at a time of request of the each timed trigger, and
reset the respective valid flag at a time of completion of the each timed trigger.