| CPC G06F 1/08 (2013.01) [G06F 5/08 (2013.01)] | 14 Claims |
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9. An asynchronous finite state machine, comprising:
a core comprising:
a destination state cell that generates a destination state signal; and
a source state cell that generates a source state signal, wherein the source state cell is configured to cause transition of the source state signal in response to an acknowledgement signal indicating transition of the destination state signal;
wherein the acknowledgment signal is communicated to the source state cell through a delay circuit; and
wherein a state overlap time is an elapsed time between transition of the destination signal state and transition of the source state signal in response to the acknowledgement signal indicating the transition of the destination state signal; and
an output net receiving inputs from the core, the output net comprising:
a balanced logic tree receiving inputs, including the destination state signal, from the core; and
an additional logic tree cascaded with the balanced logic tree to form an unbalanced logic tree such that at least one input to the additional logic tree is provided by output from the balanced logic tree, another input to the additional logic tree receiving the source state signal from the core;
wherein a tree propagation time is an elapsed time between receipt of a transition in the destination state signal by the balanced logic tree and a resulting transition of the output from the balanced logic tree provided to the additional logic tree; and
wherein the delay circuit causes the state overlap time to exceed the tree propagation time.
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