| CPC G05F 3/205 (2013.01) [G05F 3/242 (2013.01)] | 14 Claims |
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1. A compound semiconductor integrated circuit comprising biasing circuitry for generating a bias voltage at a bias output node and at least a first circuit component biased by the bias voltage at the bias output node to set an operating bias point of the first circuit component, the biasing circuitry comprising: a first circuit branch configured to extend between a defined voltage and a supply voltage, the first circuit branch comprising:
a first transistor configured as a current source to generate a defined current in the first circuit branch;
a controllably variable resistance, wherein the bias output node is coupled to the first circuit branch at a first node which is between the controllably variable resistance and the first transistor, wherein the biasing circuitry is operable so that a resistance value of the controllably variable resistance varies with a control voltage so as to vary a value of the bias voltage, wherein the first transistor of the biasing circuitry has matching characteristics to the first circuit component so as exhibit a matched response to at least one of process, temperature and voltage variations; and
a control voltage terminal for receiving the control voltage and a hardware mode select terminal, wherein the hardware mode select terminal is connected to a second node of the first circuit branch which is between the first node and the controllably variable resistance, wherein the biasing circuitry is operable:
in a hardware set mode, with the control voltage terminal left floating the hardware mode select terminal connected to the defined voltage, to generate the bias voltage as a fixed defined bias voltage; and
in a variable mode, with the control voltage terminal connected to receive the control voltage and the hardware mode select terminal left floating, to generate the bias voltage based on the control voltage.
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