US 12,135,573 B2
Low dropout regulator
Shahbaz Abbasi, Hsinchu County (TW)
Assigned to KEY ASIC INC., Hsinchu County (TW)
Filed by Key ASIC Inc., Hsinchu County (TW)
Filed on Jun. 20, 2022, as Appl. No. 17/844,216.
Prior Publication US 2023/0409061 A1, Dec. 21, 2023
Int. Cl. G05F 1/565 (2006.01); G05F 1/46 (2006.01); G05F 3/26 (2006.01)
CPC G05F 1/565 (2013.01) [G05F 1/468 (2013.01); G05F 3/262 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A low dropout regulator, comprising:
a first gain-stage, configured to generate a first signal at a first gain-stage terminal based on a second signal at a second gain-stage terminal;
a second gain-stage, electrically connected to the first gain-stage terminal, configured to receive the first signal at the first gain-stage terminal and generate a third signal at a sensing terminal;
an output setting stage, electrically connected to the first gain-stage terminal and the sensing terminal, configured to output a load current to an output terminal, wherein the third signal at the sensing terminal is changed with the load current; and
a Miller circuit, electrically connected to the first gain-stage, the second gain-stage, and the output setting stage, configured to provide a capacitance related to a dominant pole of the low dropout regulator, wherein the capacitance is changed with the third signal at the sensing terminal;
wherein the first gain-stage comprises:
a first first-stage transistor, electrically connected to the first gain-stage terminal; and
a second first-stage transistor, electrically connected to the first gain-stage terminal and the second gain-stage terminal, wherein the first signal at the first gain-stage terminal is changed with a first gain-stage current flowing through the first first-stage transistor and the second first-stage transistor; or
wherein the output setting stage comprises:
a first power transistor, electrically connected to the first gain-stage terminal and the output terminal, configured to be selectively switched on in response to the first signal at the first gain-stage terminal; and
a second power transistor, electrically connected to the sensing terminal and the output terminal, configured to be selectively switched on in response to the third signal at the sensing terminal, wherein a fourth signal at the output terminal is changed with switching statuses of the first power transistor and the second power transistor.