US 12,135,542 B2
Modelling and prediction of virtual inline quality control in the production of memory devices
Tsuyoshi Sendoda, Kuwana (JP); Yusuke Ikawa, Yokohama (JP); Nagarjuna Asam, Fujisawa (JP); Kei Samura, Yokohama (JP); and Masaaki Higashitani, Cupertino, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Nov. 2, 2022, as Appl. No. 17/979,142.
Application 17/979,142 is a continuation in part of application No. 17/725,695, filed on Apr. 21, 2022, granted, now 12,009,269.
Application 17/725,695 is a continuation in part of application No. 17/360,573, filed on Jun. 28, 2021.
Prior Publication US 2023/0054342 A1, Feb. 23, 2023
Int. Cl. G05B 19/418 (2006.01)
CPC G05B 19/41875 (2013.01) [G05B 19/4188 (2013.01); G05B 19/41885 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving inline quality control data of test samples from manufacture of an integrated circuit;
receiving post-manufacturing test data of the test samples;
creating a first virtual inline quality control data model for the manufacture of the integrated circuit from the inline quality control data and the post-manufacturing test data;
interpolating virtual inline quality control data for the manufacture of the integrated circuit from the first virtual inline quality control data model and the post-manufacturing test data;
receiving an inline data report for the manufacture of the integrated circuit;
creating a second virtual inline quality control data model for the manufacture of the integrated circuit from the interpolated virtual inline quality control data and the inline data report; and
interpolating virtual inline quality control data for the manufacture of the integrated circuit from the second virtual inline quality control data model and the inline data report.