US 12,135,460 B2
Stackable photonics die with direct optical interconnect
Todd R. Coons, Hillsboro, OR (US); Michael Rutigliano, Hillsboro, OR (US); Joe F. Walczyk, Tigard, OR (US); and Abram M. Detofsky, Tigard, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/132,912.
Prior Publication US 2022/0196915 A1, Jun. 23, 2022
Int. Cl. G02B 6/42 (2006.01); G02B 6/12 (2006.01); G02B 6/30 (2006.01); G02B 6/34 (2006.01); H01L 25/075 (2006.01); H01L 33/58 (2010.01); H01L 33/62 (2010.01); H01L 23/367 (2006.01); H04B 10/40 (2013.01)
CPC G02B 6/4201 (2013.01) [G02B 6/34 (2013.01); H01L 25/0756 (2013.01); H01L 33/62 (2013.01); G02B 6/12019 (2013.01); G02B 6/30 (2013.01); H01L 23/367 (2013.01); H01L 33/58 (2013.01); H04B 10/40 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A photonics die comprising:
a first side of the photonics die and a second side of the photonics die opposite the first side of the photonics die;
an optical interconnect at the second side of the photonics die to transmit light signals to or to receive light signals from outside the photonics die;
a photonics integrated circuit (PIC) optically coupled with the optical interconnect;
one or more electrical connectors on the first side of the photonics die, wherein the one or more electrical connectors are electrically coupled with the PIC; and
electrical circuitry to electrically couple a first location on the first side of the photonics die with a second location on the first side of the photonics die, wherein a first chip is to be disposed and electrically coupled with the first location on the first side of the photonics die, and wherein a second chip is to be disposed and electrically coupled with the second location on the first side of the photonics die.