| CPC G01R 31/316 (2013.01) [G01R 31/31704 (2013.01)] | 23 Claims |
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1. An integrated circuit comprising:
a first functional analog pin or pad;
a first analog test bus coupled to the first functional analog pin or pad;
a plurality of analog-to-digital converters (ADCs) having first inputs coupled to the first analog test bus;
a plurality of digital-to-analog converters (DACs) having outputs coupled to the first analog test bus;
a plurality of comparators having first inputs coupled to the first analog test bus:
a first analog circuit coupled to the first analog test bus, the first analog circuit comprising a DAC of the plurality of DACs, an ADC of the plurality of ADCs, or a comparator of the plurality of comparators;
a second analog circuit coupled to the first analog test bus; and
a test controller configured to:
when the integrated circuit is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus,
when the integrated circuit is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus connect the respective first inputs of each of the plurality of comparators to the first analog test bus,
provide an analog signal to the first analog test bus with the output of a first DAC in response to the first inputs of the plurality of ADCs and the first inputs of the plurality of comparators being connected to the first analog test bus, and
determine whether a comparator has a fault based on respective outputs of the plurality of comparators.
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