US 12,134,555 B2
Method and structure for CMOS-MEMS thin film encapsulation
Yu-Chia Liu, Kaohsiung (TW); Chia-Hua Chu, Zhubei (TW); and Chun-Wen Cheng, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 11, 2023, as Appl. No. 18/315,799.
Application 15/860,357 is a division of application No. 15/066,799, filed on Mar. 10, 2016, granted, now 9,868,628, issued on Jan. 16, 2018.
Application 18/315,799 is a continuation of application No. 16/908,243, filed on Jun. 22, 2020, granted, now 11,667,517.
Application 16/908,243 is a continuation of application No. 15/860,357, filed on Jan. 2, 2018, granted, now 10,689,247, issued on Jun. 23, 2020.
Prior Publication US 2023/0278856 A1, Sep. 7, 2023
Int. Cl. B81B 7/00 (2006.01); B81C 1/00 (2006.01)
CPC B81B 7/0006 (2013.01) [B81B 7/0051 (2013.01); B81C 1/00246 (2013.01); B81B 2201/0257 (2013.01); B81B 2201/0264 (2013.01); B81B 2201/0271 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/0133 (2013.01); B81C 2201/0176 (2013.01); B81C 2201/0181 (2013.01); B81C 2201/112 (2013.01); B81C 2203/0714 (2013.01); B81C 2203/0735 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a micro-electromechanical system (MEMS) device, the method comprising:
forming an insulating layer over a substrate, the insulating layer comprising a plurality of first layers and a plurality of second layers interleaved with the plurality of first layers;
forming, in a MEMS device region of the insulating layer, a dummy interconnect structure, comprising:
forming a first plurality of conductive vias in a first subset of the plurality of first layers of the insulating layer; and
forming a first plurality of metal features in a first subset of the plurality of second layers of the insulating layer, wherein the first plurality of conductive vias and the first plurality of metal features are interleaved and interconnected, wherein an uppermost layer of the first plurality of conductive vias is exposed at an upper surface of the insulating layer distal from the substrate;
after forming the dummy interconnect structure, forming a metal layer over the upper surface of the insulating layer, wherein the metal layer contacts the uppermost layer of the first plurality of conductive vias;
after forming the metal layer, performing a wet etching process, wherein the wet etching process removes the metal layer and the dummy interconnect structure, and forms void regions in the insulating layer, wherein the void regions correspond to empty spaces left by the removal of the dummy interconnect structure; and
sealing the void regions by forming sealing structures over the upper surface of the insulating layer.