US 8,115,315 C1 (12,762nd)
Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same
Jong-Joo Lee, Gyeonggi-do (KR)
Filed by Jong-Joo Lee, Gyeonggi-do (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Reexamination Request No. 90/015,304, Sep. 29, 2023.
Reexamination Certificate for Patent 8,115,315, issued Feb. 14, 2012, Appl. No. 12/431,956, Apr. 29, 2009.
Application 90/015,304 is a division of application No. 11/378,899, filed on Mar. 17, 2006, granted, now 7,545,037.
Claims priority of application No. 2005-002787 (KR), filed on Mar. 18, 2005.
Ex Parte Reexamination Certificate issued on Oct. 31, 2024.
Int. Cl. H01L 23/528 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/5286 (2013.01) [H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H10B 12/09 (2023.02); H01L 2224/05548 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05571 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/0002 (2013.01)]
OG exemplary drawing
AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT:
Claims 1-21 are cancelled.
1. A semiconductor chip comprising:
a semiconductor substrate having an internal circuit at an upper portion thereof;
an internal interconnection disposed on the semiconductor substrate and electrically connected to the internal circuit;
a chip pad disposed on the semiconductor substrate and electrically connected to the internal circuit by the internal interconnection;
a passivation layer extending over the substrate; and
a redistributed metal interconnection extending over the passivation layer, and wherein one portion of the redistributed metal interconnection passes through the passivation layer and is electrically conductively connected to the internal interconnection, and another portion of the redistributed metal interconnection passes through the passivation layer and is electrically conductively connected to the chip pad such that the internal interconnection and the chip pad are electrically connected to one another by the redistributed metal interconnection,
wherein the internal connection and the chip pad are formed at a same level relative to a surface of the semiconductor substrate.