| CPC H10D 84/853 (2025.01) [H10D 30/795 (2025.01); H10D 30/797 (2025.01); H10D 62/116 (2025.01); H10D 62/126 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01)] | 11 Claims |
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[ 12. A semiconductor device comprising:
a first element isolating area made of an insulating material;
a first element area surrounding sides of the first element isolating area, and including first to fourth regions, the first and second regions extending in a first direction, the third and fourth regions extending in a second direction orthogonal to the first direction, the first region being connected to one end portion of the third region and one end portion of the fourth region, the second region being connected to the other end portion of the third region and the other end portion of the fourth region,
the first region having a first source/drain region, a first channel region and a second source/drain region arranged in this order along first direction, and
the second region including a third source/drain region, a second channel region and a fourth source/drain region arranged in this order along first direction;
a first gate electrode provided on and across the first element isolating area and the first channel region of the first region, the first gate electrode extending in the second direction and having a first end;
a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area and the first channel region of the second region, the second gate electrode extending in the second direction and having a second end facing the first end;
a first gate insulation film provided between the first region and the first gate electrode; a second gate insulation film provided between the second region and the second gate electrode;
a second element isolating area made of an insulating material;
a second element area surrounding sides of the second element isolating area;
a third gate electrode provided on and across the second element isolating area and the second element area; and
a fourth gate electrode isolated from the third gate electrode and provided on and across the second element isolating area and the second element area, wherein
the first gate electrode and the first element area form a first transistor,
the second gate electrode and the first element area form a second transistor,
a channel length direction of the first transistor is aligned in the first direction,
a channel length direction of the second transistor is aligned in the first direction,
the channel length directions of the first and second transistors are shifted from each other when viewed in the first direction,
the first element area forms a substantially rectangular annular shape,
the second element area forms a substantially rectangular annular shape,
a transistor of a first conductive-type is formed by the first gate electrode and the first element area, and a transistor of a second conductive-type which is different from the first conductive-type is formed by the third gate electrode and the second element area, and
the first element area and the second element area are different from each other in outer dimension in the first direction. ]
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