| CPC H10N 50/10 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |

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1. A semiconductor device comprising:
a first conductive feature on a semiconductor substrate;
a bottom electrode on the first conductive feature;
a magnetic tunnel junction (MTJ) stack on the bottom electrode, the MTJ stack comprising:
a reference layer on the bottom electrode;
a tunnel barrier layer on the reference layer; and
a free layer on the reference layer;
a first spacer in contact with a side surface of the free layer and a side surface of the tunnel barrier layer, wherein a bottom surface of the first spacer is level with a bottom surface of the tunnel barrier layer;
a second spacer adjacent the first spacer and has a bottom surface nearer the semiconductor substrate than a bottom surface of the first spacer; and
a top electrode on the MTJ stack.
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