| CPC H10H 20/857 (2025.01) [H10H 20/821 (2025.01); H10H 20/831 (2025.01); H10H 20/835 (2025.01); H10H 20/84 (2025.01); H10H 20/856 (2025.01)] | 17 Claims |
|
1. A light emitting element comprising:
a semiconductor stack structure comprising:
a first semiconductor layer of a first conductivity type, wherein, in a top plan view, the first semiconductor layer has a first portion, and a second portion positioned within the first portion, and wherein, in a top plan view, the first semiconductor layer has a quadrangular shape including a first side, a second side connected to the first side, a third side connected to the second side, and a fourth side connected to the first and third sides,
a second semiconductor layer of a second conductivity type disposed on the second portion, and
an active layer disposed between the first semiconductor layer and the second semiconductor layer,
wherein the first portion has a peripheral portion positioned at a periphery of the second portion, and exactly four extended portions, which are a first extended portion opposing the first side, a second extended portion opposing the second side, a third extended portion opposing the third side, and a fourth extended portion opposing the fourth side, wherein each extended portion extends from the peripheral portion towards the second portion in a top plan view;
an insulation layer covering the semiconductor stack structure and having first through holes individually positioned in the extended portions and a second through hole positioned above the second semiconductor layer;
a first electrode disposed on the second semiconductor layer via the insulation layer and electrically connected to the first semiconductor layer at the first through holes;
a second electrode electrically connected to the second semiconductor layer at the second through hole;
a first external connection part disposed on the first electrode positioned above the second semiconductor layer and electrically connected to the first electrode; and
a second external connection part disposed on the second electrode and electrically connected to the second electrode; wherein:
in a top plan view, the second semiconductor layer includes four regions defined by two imaginary lines, a first imaginary line being orthogonal to and halving the first side and a second imaginary line being orthogonal to and halving the second side;
the four regions include:
a first region in which the first external connection part is disposed,
a second region adjacent to the first region in a first direction parallel to the second side,
a third region adjacent to the first region in a second direction parallel to the first side, and
a fourth region adjacent to the second region in the second direction, in which the second external connection part is disposed;
the first and third extended portions are positioned on the first imaginary line; and
the second and fourth extended portions are positioned on the second imaginary line.
|