US 12,464,863 B2
Epitaxial oxide transistor
Petar Atanackovic, Henley Beach South (AU)
Assigned to Silanna UV Technologies Pte Ltd, Singapore (SG)
Filed by Silanna UV Technologies Pte Ltd, Singapore (SG)
Filed on Apr. 8, 2024, as Appl. No. 18/629,555.
Application 18/629,555 is a continuation of application No. 17/652,019, filed on Feb. 22, 2022, granted, now 12,087,880.
Application 17/652,019 is a continuation of application No. PCT/IB2021/060466, filed on Nov. 11, 2021.
Application PCT/IB2021/060466 is a continuation in part of application No. PCT/IB2021/060414, filed on Nov. 10, 2021.
Application PCT/IB2021/060466 is a continuation in part of application No. PCT/IB2021/060427, filed on Nov. 10, 2021.
Application PCT/IB2021/060466 is a continuation in part of application No. PCT/IB2021/060413, filed on Nov. 10, 2021.
Prior Publication US 2024/0266469 A1, Aug. 8, 2024
Int. Cl. H10H 20/822 (2025.01); H01L 21/02 (2006.01); H01L 23/66 (2006.01); H01S 5/34 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 62/815 (2025.01); H10D 62/82 (2025.01); H10D 62/85 (2025.01); H10D 64/68 (2025.01); H10H 20/01 (2025.01); H10H 20/811 (2025.01); H10H 20/812 (2025.01); H10H 20/817 (2025.01); H10H 20/818 (2025.01); H10H 20/857 (2025.01); H10H 29/10 (2025.01)
CPC H10H 20/822 (2025.01) [H01L 21/02178 (2013.01); H01L 21/02192 (2013.01); H01L 21/02194 (2013.01); H01L 21/0228 (2013.01); H01L 21/02458 (2013.01); H01L 21/02507 (2013.01); H01L 23/66 (2013.01); H01S 5/34 (2013.01); H10D 30/015 (2025.01); H10D 30/6755 (2025.01); H10D 62/80 (2025.01); H10D 62/8161 (2025.01); H10D 62/82 (2025.01); H10D 62/8503 (2025.01); H10D 64/691 (2025.01); H10H 20/01335 (2025.01); H10H 20/811 (2025.01); H10H 20/812 (2025.01); H10H 20/817 (2025.01); H10H 20/818 (2025.01); H10H 20/857 (2025.01); H10H 29/10 (2025.01); H01L 2223/6627 (2013.01); H10D 30/47 (2025.01); H10D 30/475 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a substrate comprising sapphire;
an epitaxial channel layer on the substrate, the epitaxial channel layer comprising α-Ga2O3 with a first bandgap;
an epitaxial gate layer on the epitaxial channel layer, the epitaxial gate layer comprising an oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and
electrical contacts comprising:
a source electrical contact coupled to the epitaxial channel layer;
a drain electrical contact coupled to the epitaxial channel layer; and
a gate electrical contact coupled to the epitaxial gate layer.