US 12,464,849 B2
Solar cell emitter region fabrication with differentiated p-type and n-type architectures and incorporating a multi-purpose passivation and contact layer
Staffan Westerberg, Sunnyvale, CA (US); and Seung Bum Rim, Palo Alto, CA (US)
Assigned to Maxeon Solar Pte. Ltd., Singapore (SG)
Filed by Maxeon Solar Pte. Ltd., Singapore (SG)
Filed on Jul. 15, 2024, as Appl. No. 18/773,281.
Application 18/773,281 is a division of application No. 15/362,045, filed on Nov. 28, 2016, granted, now 12,074,232.
Application 15/362,045 is a continuation of application No. 14/671,781, filed on Mar. 27, 2015, granted, now 9,525,083, issued on Dec. 20, 2016.
Prior Publication US 2024/0372016 A1, Nov. 7, 2024
Int. Cl. H01L 31/00 (2006.01); H10F 10/14 (2025.01); H10F 71/00 (2025.01); H10F 71/10 (2025.01); H10F 77/122 (2025.01); H10F 77/1223 (2025.01); H10F 77/164 (2025.01); H10F 77/166 (2025.01); H10F 77/20 (2025.01); H10F 77/30 (2025.01); H10F 77/70 (2025.01)
CPC H10F 77/311 (2025.01) [H10F 10/146 (2025.01); H10F 71/103 (2025.01); H10F 71/1221 (2025.01); H10F 71/129 (2025.01); H10F 77/122 (2025.01); H10F 77/1223 (2025.01); H10F 77/1642 (2025.01); H10F 77/1662 (2025.01); H10F 77/219 (2025.01); H10F 77/315 (2025.01); H10F 77/703 (2025.01); Y02E 10/546 (2013.01); Y02E 10/547 (2013.01); Y02E 10/548 (2013.01); Y02P 70/50 (2015.11)] 15 Claims
OG exemplary drawing
 
1. A method of fabricating alternating N-type and P-type emitter regions of a solar cell, the method comprising:
forming an N-type silicon layer on a first thin dielectric layer formed on a back surface of a substrate;
forming an insulating layer on the N-type silicon layer;
patterning the insulating layer and the N-type silicon layer to form N-type silicon regions having an insulating cap thereon;
forming a second thin dielectric layer on exposed sides of the N-type silicon regions;
forming a P-type silicon layer on a third thin dielectric layer formed on the back surface of the substrate, and on the second thin dielectric layer and the insulating cap of the N-type silicon regions;
forming a P-type amorphous silicon layer on the P-type silicon layer;
patterning the P-type amorphous silicon layer and the P-type silicon layer to form isolated P-type emitter regions and to form contact openings in regions of the P-type amorphous silicon layer and the P-type silicon layer above the insulating cap of the N-type silicon regions;
patterning the insulating cap through the contact openings to expose portions of the N-type silicon regions; and
forming conductive contacts to the N-type silicon regions and to the P-type emitter regions, the conductive contacts to the N-type silicon regions formed in the contact openings, and the conductive contacts to the P-type emitter regions formed in direct contact with the P-type amorphous silicon layer of the P-type emitter regions.