US 12,464,846 B2
Image sensor
Minho Jang, Suwon-si (KR); and Seungkuk Kang, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 1, 2022, as Appl. No. 17/901,335.
Claims priority of application No. 10-2021-0122069 (KR), filed on Sep. 13, 2021.
Prior Publication US 2023/0081238 A1, Mar. 16, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 23/00 (2006.01); H10F 39/00 (2025.01); H10F 39/18 (2025.01)
CPC H10F 39/811 (2025.01) [H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H10F 39/018 (2025.01); H10F 39/809 (2025.01); H01L 24/80 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/0903 (2013.01); H01L 2224/09181 (2013.01); H01L 2224/8082 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01); H10F 39/18 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An image sensor comprising:
a stack structure comprising an active pixel region in which a plurality of pixels are defined, and a pad region arranged on at least one side of the active pixel region,
wherein each of the plurality of pixels includes a photoelectric conversion region and a floating diffusion region,
wherein the stack structure comprises:
a first substrate comprising:
a first semiconductor substrate at which the photoelectric conversion region and the floating diffusion region in each of the plurality of pixels are disposed, the first semiconductor substrate comprising a first surface and a second surface,
a first front structure arranged on the first surface of the first semiconductor substrate, and
a pad opening penetrating the first semiconductor substrate in the pad region;
a second substrate attached to the first substrate and comprising a plurality of pixel gates, each of the plurality of pixel gates being electrically connected to a floating diffusion region in a corresponding pixel of the plurality of pixels;
a third substrate attached to the second substrate and comprising a logic transistor for driving the plurality of pixels; and
a pad having a top surface that is exposed through the pad opening, and
wherein the top surface of the pad is arranged at a lower vertical level than the first surface of the first semiconductor substrate and at a higher vertical level than a bottom surface of the third substrate.