US 12,464,841 B2
Semiconductor apparatus and semiconductor apparatus manufacturing method
Toshihiko Miyazaki, Kanagawa (JP); Yuki Kawahara, Kanagawa (JP); Tsuyoshi Suzuki, Kanagawa (JP); and Tadashi Iijima, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/620,901
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jun. 26, 2020, PCT No. PCT/JP2020/025146
§ 371(c)(1), (2) Date Dec. 20, 2021,
PCT Pub. No. WO2020/262583, PCT Pub. Date Dec. 30, 2020.
Claims priority of application No. 2019-119167 (JP), filed on Jun. 26, 2019.
Prior Publication US 2022/0352226 A1, Nov. 3, 2022
Int. Cl. H01L 27/14 (2006.01); H10F 39/00 (2025.01)
CPC H10F 39/8057 (2025.01) [H10F 39/018 (2025.01); H10F 39/024 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01)] 25 Claims
OG exemplary drawing
 
1. A semiconductor apparatus, comprises:
a first substrate that includes:
a first element layer that includes a first active element;
a first wiring layer on the first element layer; and
a shield layer on the first wiring layer, wherein the shield layer includes:
an electrically conductive material; and
a plurality of openings; and
a second substrate that includes:
an interlayer dielectric film on the shield layer;
a second element layer that includes a second active element; and
a second wiring layer on the second element layer, wherein
the second element layer is on the interlayer dielectric film,
the interlayer dielectric film is in between the plurality of openings, and
the second substrate is on the first substrate.