US 12,464,827 B2
Resistor with exponential-weighted trim
Steve Edward Harrell, Corinth, TX (US); Keith Eric Sanborn, Tucson, AZ (US); Wai Lee, Dallas, TX (US); and Erika Lynn Mazotti, San Martin, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 15, 2021, as Appl. No. 17/376,747.
Application 17/376,747 is a division of application No. 16/547,615, filed on Aug. 22, 2019, granted, now 11,101,263.
Claims priority of provisional application 62/725,724, filed on Aug. 31, 2018.
Claims priority of provisional application 62/725,980, filed on Aug. 31, 2018.
Prior Publication US 2021/0343694 A1, Nov. 4, 2021
Int. Cl. H10D 84/00 (2025.01); H01L 23/525 (2006.01); H10D 99/00 (2025.01); H10D 1/47 (2025.01)
CPC H10D 99/00 (2025.01) [H01L 23/5256 (2013.01); H01L 23/5258 (2013.01); H10D 84/209 (2025.01); H10D 1/47 (2025.01)] 26 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit, comprising:
forming a plurality of unit resistors in a semiconductor substrate;
connecting a first subset N of the unit resistors in series thereby forming a first composite resistor;
connecting a second subset N of the unit resistors in parallel thereby forming a second composite resistor;
connecting a first terminal of the first composite resistor and a first terminal of the second composite resistor to a first interconnection bus;
connecting a second terminal of the first composite resistor and a second terminal of the second composite resistor to a second interconnection bus; and
connecting a first fusible link between the second interconnection bus and the first composite resistor, and connecting a second fusible link between the second interconnection bus and the second composite resistor.