US 12,464,826 B2
Semiconductor device
Yasuyuki Morishita, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Oct. 12, 2022, as Appl. No. 17/964,267.
Claims priority of application No. 2021-178382 (JP), filed on Oct. 29, 2021; and application No. 2022-126689 (JP), filed on Aug. 8, 2022.
Prior Publication US 2023/0139094 A1, May 4, 2023
Int. Cl. H01L 27/02 (2006.01); H10D 89/10 (2025.01); H10D 89/60 (2025.01)
CPC H10D 89/611 (2025.01) [H10D 89/10 (2025.01); H10D 89/601 (2025.01); H10D 89/921 (2025.01); H10D 89/931 (2025.01)] 2 Claims
OG exemplary drawing
 
1. A semiconductor device in which an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit are arranged on a chip,
wherein the core power supply cell includes an ESD protection circuit,
wherein the input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell,
wherein the core logic circuit is arranged outside the input/output cell,
wherein the core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged, and
wherein the core power supply cell is formed such that a long side of external dimensions thereof is shorter than a long side of an outer shape of the IO power supply cell, and a short side of external dimensions thereof is equal to or greater than a short side of the outer shape of the IO power supply cell.