| CPC H10D 84/907 (2025.01) [H10D 89/10 (2025.01); H10D 84/912 (2025.01); H10D 84/921 (2025.01); H10D 84/966 (2025.01); H10D 84/975 (2025.01); H10D 84/981 (2025.01); H10D 84/987 (2025.01)] | 12 Claims |
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1. An integrated circuit comprising:
a first power rail and a second power rail disposed in parallel and spaced apart in a first direction; and
a first standard cell, a second standard cell and a third standard cell,
wherein the first to the third standard cells are disposed between the first power rail and the second power rail and disposed adjacent to each other in a second direction,
wherein each of the first standard cell, the second standard cell and the third standard cell includes:
a first-type active region extended in the second direction;
a second-type active region extended in the second direction and spaced apart from the first-type active region in the first direction;
first-type transistors disposed in the first-type active region; and
second-type transistors disposed in the second-type active region,
wherein first source contacts of the first-type transistors are independently connected to the first power rail and are separated from each other,
wherein second source contacts of the second-type transistors are independently connected to the second power rail and are separated from each other,
wherein the second standard cell includes drain contacts, and
wherein one of drain contacts of the first-type transistors or one of drain contacts of the second-type transistors in the first standard cell is commonly connected to one of the drain contacts in the second standard cell through a via.
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