US 12,464,820 B2
Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
Mou-Shiung Lin, Hsinchu (TW); and Jin-Yuan Lee, Miaoli County (TW)
Assigned to iCometrue Company Ltd., Hsinchu County (TW)
Filed by iCometrue Company Ltd., Zhubei (TW)
Filed on Dec. 10, 2023, as Appl. No. 18/534,689.
Application 18/534,689 is a continuation of application No. 17/710,979, filed on Mar. 31, 2022, granted, now 11,881,483.
Application 17/710,979 is a continuation of application No. 17/100,937, filed on Nov. 22, 2020, granted, now 11,309,334, issued on Apr. 19, 2022.
Application 17/100,937 is a continuation in part of application No. 16/565,967, filed on Sep. 10, 2019, granted, now 10,892,011, issued on Jan. 12, 2021.
Claims priority of provisional application 62/869,567, filed on Jul. 2, 2019.
Claims priority of provisional application 62/729,527, filed on Sep. 11, 2018.
Prior Publication US 2024/0105729 A1, Mar. 28, 2024
Int. Cl. H10D 84/90 (2025.01); G11C 14/00 (2006.01); H01L 23/48 (2006.01); G11C 5/04 (2006.01)
CPC H10D 84/907 (2025.01) [G11C 5/04 (2013.01); G11C 14/0081 (2013.01); H10D 84/938 (2025.01); H10D 84/975 (2025.01)] 26 Claims
OG exemplary drawing
 
1. A chip package comprising:
an element comprising a first silicon substrate, a first through silicon via vertically in the first silicon substrate, wherein the first through silicon via comprises a first copper layer vertically in the first silicon substrate and a first adhesion metal layer at a sidewall of the first copper layer, a first silicon-oxide-containing layer over the first silicon substrate, and a first bonding pad in a first opening in the first silicon-oxide-containing layer and coupling to the through silicon via, wherein the first bonding pad comprises a second copper layer in the first opening in the first silicon-oxide-containing layer and a second adhesion metal layer having a first portion at a sidewall of the second copper layer and a second portion at a bottom of the second copper layer;
a first semiconductor chip over and bonded to the element, wherein the first semiconductor chip comprises a second silicon substrate, a transistor at a bottom of the second silicon substrate, a first interconnection metal layer under the second silicon substrate, a second silicon-oxide-containing layer under the second silicon substrate and first interconnection metal layer and a second bonding pad under and on the first interconnection metal layer and in a second opening in the second silicon-oxide-containing layer, wherein the first interconnection metal layer comprises a third copper layer and a third adhesion metal layer having a first portion at a sidewall of the third copper layer and a second portion at a top of the third copper layer, and wherein the second bonding pad comprises a fourth copper layer in the second opening in the second silicon-oxide-containing layer and a fourth adhesion metal layer having a first portion at a sidewall of the fourth copper layer and a second portion at a top of the fourth copper layer, between the fourth copper layer and first interconnection metal layer and in contact with the first interconnection metal layer, wherein the fourth copper layer has a bottom surface bonded to and in contact with a top surface of the second copper layer and the second silicon-oxide-containing layer has a bottom surface bonded to and in contact with a top surface of the first silicon-oxide-containing layer, wherein the element couples to the first semiconductor chip through the first and second bonding pads; and
a sealing layer over the element and at a same horizontal level as the first semiconductor chip.