US 12,464,818 B2
Three-dimensional semiconductor device having vertical misalignment
Inchan Hwang, Schenectady, NY (US); Seunghyun Song, Albany, NY (US); and Byounghak Hong, Latham, NY (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 4, 2024, as Appl. No. 18/732,767.
Application 18/732,767 is a continuation of application No. 17/500,618, filed on Oct. 13, 2021, granted, now 12,040,327.
Claims priority of provisional application 63/231,967, filed on Aug. 11, 2021.
Prior Publication US 2024/0363634 A1, Oct. 31, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/85 (2025.01); H01L 21/02 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/856 (2025.01) [H01L 21/0259 (2013.01); H01L 23/535 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A multi-stack semiconductor device comprising:
a first transistor structure comprising a first channel structure and a first gate structure on the first channel structure;
a second transistor structure comprising a second channel structure and a second gate structure on the second channel structure, the second transistor being disposed above the first transistor in a first direction; and
a gate contact plug contacting the second gate structure and a top surface of the first gate structure facing a bottom surface of the second gate structure.